The present invention relates to apparatus for recording and reproducing video signals and, more particularly, to recording, reproducing and dubbing video signals which include video information and copy protection information for restricting the number of times the video information is copied.
In video recording and reproducing apparatus, such as a video cassette recorder (VCR) or a camcorder, input video signals and input audio signals are processed and recorded on a recording medium, such as a tape, for subsequent reproduction. FIG. 1 is a block diagram of a proposed signal processing circuit of the recording side of a digital recording and reproducing device and is described in copending application Ser. No. 08/304,878, filed Feb. 7, 1995.
As shown in FIG. 1, an analog composite video signal, which, for example, is comprised of video signals Y, R-Y, and B-Y, is supplied to an A/D processing circuit 1, which converts the analog composite video signal to a digital video signal and delivers the signal to a blocking/shuffling circuit 2.
The blocking/shuffling circuit 2 samples the data in an effective scan area of one frame of the digital composite video signal (that is, an area which contains viewable information) and arranges the samples into units. As an example, the Y, R-Y, and B-Y components of the digital composite video signal of the frame are respectively divided into a predetermined number of horizontal samples and into a predetermined number of vertical samples, and the samples are grouped into units formed of eight horizontal samples by eight vertical samples.
The blocking/shuffling circuit 2 supplies the units to a Discrete Cosine Transform (DCT) circuit 3 which transforms the units into DCT units and delivers the DCT units to encoding circuit 4. The encoding circuit 4 quantizes the DCT units and variable length encodes the quantized DCT units using, for example, a two-dimensional Huffman code. The encoding circuit 4 quantizes the DCT units in buffering units of 30 DCT units each, for example, so that the length of the variable length encoded output of the encoding circuit 4 is within a predefined value.
The operation of the blocking/shuffling circuit 2, Discrete Cosine Transform (DCT) circuit 3 and the encoding circuit 4 are known in the art and are not further described.
The encoding circuit 4 delivers the variable length encoded output to a framing circuit 5, which forms blocks of video signals in a predefined format from the variable length encoded output. The blocks of video signals are delivered to a switching circuit 6 which comprises a multiplexing circuit or a multiplexing/demultiplexing circuit.
An input analog audio signal is converted to a digital audio signal by an A/D processing circuit 7 which delivers the digital audio signal to an interleaving circuit 8. The interleaving circuit 8 interleaves the digital audio signal so that the effect of burst errors on the sound quality is minimized and then delivers the interleaved audio signal to the switching circuit 6.
A microprocessor 10 generates and delivers accompanying audio and video information to an accompanying (AUX) data generating circuit 11 which forms blocks of accompanying video signals, such as formatted VAUX signals, and blocks of accompanying audio signals, such as formatted AAUX signals, under the control of the microprocessor 10. VAUX and AAUX signals are described in application Ser. No. 08/384,879. The AUX data generating circuit 11 delivers the formatted VAUX signals and the formatted AAUX signals to the switching circuit 6.
The microprocessor 10 generates and delivers subcode information, used for high-speed searching of the recording medium, to a subcode generating circuit 13 which generates formatted subcode signals under the control of the microprocessor 10. The subcode generating circuit 13 delivers the formatted subcode signals to the switching circuit 6.
The switching circuit 6 combines the blocks of video signals and the formatted VAUX signals to form blocks of associated video signals in a first predefined format and combines the interleaved audio signals and the formatted AAUX signals to form blocks of associated audio signals in a second predefined format. The switching circuit 6 supplies the blocks of associated video signals, the blocks of associated audio signals and the formatted subcode signals to a deshuffling circuit 14.
The deshuffling circuit 14 temporarily stores the blocks of associated video signals, the blocks of associated audio signals and the formatted subcode signals in a frame memory and rearranges the blocks of associated video signals so that blocks of associated video signals that correspond to adjacent regions of the video frame are recorded on adjacent regions of the recording medium. The deshuffling circuit 14 delivers the rearranged blocks of associated video signals, the blocks of associated audio signals and the formatted subcode signals to a parity generating circuit 15 which adds an error correcting code and delivers the signals to a channel encoder 16. The channel encoder 16 signal modulates the rearranged blocks of associated video signals, the blocks of associated audio signals and the formatted subcode signals by affixing a SYNC signal to the signals, for example, and converts the signals to serial form. The channel encoder 16 supplies the signals to a recording head for recording onto a recording medium.
FIGS. 2A and 2B show a recording format for the signals formed by the processing circuit shown in FIG. 1. A plurality of helically recorded tracks form one picture frame, as shown in FIG. 2A. In the NTSC format, a frame is recorded in ten tracks, and in the PAL format a frame is recorded in 12 tracks. FIG. 2B shows the recording format for one track of the frame. The track is bounded by margins, and starting from the left most margin, which represents the recording start end, there are recorded an audio area, a video area and a subcode area. Inter-block gaps, which serve as a margin for editing and for prevention of overwriting of data, are provided between these areas.
FIGS. 3A-3D show the respective areas of one track in greater detail. The audio area, shown in FIG. 3B, is comprised of a pre-amble sector, which includes a run-up block and a pre-sync block, an audio sector and a post-amble sector, which includes post-sync and guard area blocks. The pre- and post-sync blocks include a 2 byte sync region formed by a recording signal modulating circuit (not shown) using 24 to 25 conversion, and a 3 byte ID region formed by an ID data adding circuit (not shown).
The ID region is divided into an ID0 byte, an ID1 byte and an IDP byte. The ID0 bytes, shown in greater detail in FIGS. 4A and 4B, store data such as application data bits AP1 or AP2, for indicating the data format of the sync blocks, sequencing data bits SEQ for identifying the frame number (which is useful during a variable speed playback mode) and track data bits TRACK for identifying the track number of the frame. The ID1 bytes, also shown in FIGS. 4A-4B, store sync data. The IDP byte (not shown) stores parity data.
The audio sector of the audio area, shown in FIG. 5A, is divided into 9 sync blocks of 77 bytes each. The audio sync blocks include 5 bytes of AAUX signal data, 72 bytes of audio signal data, and 8 bytes of inner parity data C1. FIG. 5B illustrates one of the nine audio sync blocks. The lower five sync blocks (shown in FIG. 5A) C2 are parity sync blocks and include outer parity data and inner parity data.
The video area, shown in FIG. 3C, includes a pre-amble sector, which includes run-up and pre-sync regions, a video sector, and a post-amble sector, which includes post-sync and guard area regions. As in the audio sector, the video sector is divided into sync blocks and each sync block includes 2 bytes of sync data and 3 bytes of ID data, shown in FIG. 6. The pre-sync blocks and the post-sync block are structured in a manner similar to the pre- and post-sync blocks of the audio sector.
The video sector of the video area is shown in detail in FIG. 6 and includes 149 sync blocks. Sync blocks .alpha., .beta. and .gamma., shown in greater detail in FIG. 7A, are VAUX sync blocks and store the accompanying video information signals. The 135 remaining sync blocks, shown in FIG. 6, include video data as well as inner parity data and form buffering units BUF0 to BUF26. The eleven sync blocks C2 are parity sync blocks and include both outer parity data and inner parity data.
FIG. 7C illustrates a buffering unit formed of five sync blocks, each comprised of the 77 bytes of video data shown in FIG. 7B. The first byte is a Q data byte in which quantization data is stored. Following the Q byte, are 76 bytes of video signal data.
The AAUX region of the audio sector of the audio area shown in FIG. 5B and the VAUX region of the video sector of the video area shown in FIG. 7A are each formed of "packs", shown in FIG. 8. The first byte PC0 of the pack serves as a pack header (ITEM) and the remaining bytes, PC1-PC4, serve as pack data.
The ITEM data is divided into upper 4-bit data and lower 4-bit data. The upper 4-bit data identifies what is referred to as a "large" item, and the lower 4-bit data identifies what is referred to as a "small" item. The upper 4-bit "large" item and the lower 4-bit "small" item define the format and content of the succeeding data. There are at most 16 "large" items, and for a respective "large" item, there are at most 16 "small" items.
The large items identified by the upper 4 bits of the item data include, as shown in FIG. 9, control 0000!, title 0001!, chapter 0010!, part 0011!, and program 0100! items. Line item 0101! indicates data recorded during a vertical blanking period. Other items include the video auxiliary (VAUX) data 0110!, the audio auxiliary (AAUX) data 0111! and soft mode data 1111!, which is designated for software applications. Large items 1000! to 1110! are reserved items for future applications.
The pack structure of the three VAUX sync blocks .alpha., .beta. and .gamma. of the video sector of the video area are shown in FIG. 10. Each VAUX sync block includes 15 5-byte packs, for a total of 45 packs per track. Similarly, nine 5-byte packs are recorded in the AAUX regions of the audio sector shown in FIG. 5A.
FIG. 11 shows the VAUX pack data structure of one frame. In an NTSC frame consisting of 10 tracks, there is a total of 450 VAUX regions, 45 per track. Of the 45 VAUX regions in each track, 6 are designated as main VAUX regions, numbered 60-65, and the remaining are designated as optional regions. In the main VAUX regions, there are recorded packs of information regarding basic data common to all tapes.
The VAUX packs formed by the VAUX large item 0110! and its respective small items include the VAUX SOURCE pack 0110 0000! (the hexadecimal representation of which is "60"), the VAUX SOURCE CONTROL pack 0110 0001! ("61"), the VAUX REC DATA pack 0110 0010! ("62"), the VAUX REC TIME pack 0110 0011! ("63") and the VAUX REC TIME BINARY GROUP pack 0110 0100! ("64").
The VAUX SOURCE CONTROL pack 0110 0001! ("61"), shown in FIG. 12B, includes a Serial Copy Management System (SCMS) code which includes copy protection information for restricting the number of times the video signals are to be copied. The upper ("copy protect") bit of the SCMS code indicates whether copying of the video signals is permitted and has a value "0" when copying is permitted and a value "1" when copying is not permitted. The value of the lower ("original") bit of the SCMS code indicates whether the video signals stored in the recording medium is the original copy ("0") or not ("1").
The VAUX SOURCE CONTROL pack also includes flag code "REC ST" which indicates whether or not a recording signal is the starting point for recording. "REC MODE" indicates whether a recorded item is an original or an after-recorded item. "FF" is a flag which indicates whether or not the video signal is a 1-field signal that is repeated to form a frame. Flag "FS" indicates whether or not the record is an odd-order field, and flag "FC" indicates whether or not the video data in a present frame is identical to the video data in the immediately preceding frame. Flag "IL" indicates whether or not the recording signal is interlaced. "ST" is a flag which indicates whether or not the recording signal is a still picture signal, and "SC" is a flag which indicates whether or not the image content to be recorded is a still picture that is reproduced with the tape travel of the reproducing VTR temporarily stopped. "BCSYS" represents the aspect ratio. "GENRE CATEGORY" is a code which represents the genre of a recorded item.
The AAUX packs formed by the AAUX large item 0101! and its respective small items include the AAUX SOURCE pack 0101 0000! (the hexadecimal representation of which is "50"), the AAUX SOURCE CONTROL pack 0101 0001! ("51"), the AAUX REC DATA pack 0101 0010! ("52"), the AAUX REC TIME pack 0101 0011! ("53") and the AAUX REC TIME BINARY GROUP pack 0101 0100! ("54").
The AAUX SOURCE CONTROL pack 0101 0001! ("51"), shown in FIG. 12A, includes the "SCMS" code which includes copy protection information for restricting the number of times the audio signals are to be copied. The upper ("copy protection") bit and the lower ("original") bit of the SCMS code exhibit the same values described above with reference to the VAUX SOURCE CONTROL pack shown in FIG. 12B.
The subcode area, shown in FIG. 3D, includes a preamble sector, a subcode sector, and a post-amble sector. The format of the subcode area is shown in detail in FIG. 13A and is further divided into 12 sync blocks 0-11, each shown in FIG. 13B. Each sync block includes 2 bytes of sync data, 3 bytes of ID data, 5 bytes of subcode pack data, and 2 bytes of parity data.
FIG. 14 is a block diagram of a reproducing side of a digital recording and reproducing device of the type described in the aforenoted application. As shown in FIG. 14, signals reproduced from the recording medium by a reproducing head (not shown) are supplied to a channel decoder 25 which converts the signals from series to parallel form and then demodulates them. The channel decoder 25 delivers the demodulated signals to an error correcting circuit 27 via a time base correcting circuit (TBC) 26. The error correcting circuit 27 error corrects the signals or, if too many errors are present in a portion of the signals, appends an error flag to that portion. The error correcting circuit 27 supplies the error corrected signals to a shuffling circuit 28 which temporarily stores the signals and rearranges the video portion of the signals into the above-described buffering units or, if an error flag is appended to the signals, replaces that portion of the signals with the buffering units of an immediately preceding portion stored in the frame memory of the shuffling circuit.
The shuffling circuit 28 supplies the shuffled signals to a switching circuit 6, comprised of a demultiplexing circuit or, preferably, a multiplexing/demultiplexing circuit, which separates the signals into signals representing the above-described video, audio and subcode areas, divides the video area signals into blocks of video signals and into blocks of VAUX signals and divides the audio area signals into blocks of audio signals and blocks of AAUX signals. The blocks of VAUX signals and the blocks of AAUX signals are formed of, for example, the packs shown in FIG. 8.
The switching circuit 6 supplies the blocks of video signals to a deframing circuit 29 which decomposes the blocks of video signals into variable length encoded video signals which are then supplied to a decoding circuit 30. The decoding circuit 30 variable length decodes and inverse quantizes the variable length encoded video signals and then supplies the decoded and dequantized signals to an inverse DCT (IDCT) circuit 31 which decompresses and supplies the decompressed video signals to a de-blocking/de-shuffling circuit 32. The de-blocking/de-shuffling circuit 32 supplies the de-shuffled video signal to a D/A conversion circuit 33 which converts the de-shuffled video signal to an analog composite video signal which is comprised of, for example, a Y signal, a R-Y signal, and a B-Y signal. The analog video signal is supplied to an output terminal and, as an example, is delivered to a display device where a reproduced image is displayed.
The switching circuit 6 supplies the blocks of audio signals to a de-interleaving circuit 34 which operates in a complementary manner to interleave circuit 8 of FIG. 1 and further processes the audio signals which then are supplied to D/A conversion circuit 35 for output as an analog audio signal.
The switching circuit 6 also supplies the blocks of VAUX and AAUX signals to an AUX data decoder 24 which decodes the accompanying audio and video information and supplies the decoded information to microprocessor 10 which performs various controlling operations as a function of the accompanying audio and video information.
The switching circuit 6 further supplies the subcode signals to a subcode data decoder 36 which decodes information from the subcode data and supplies the decoded information to the microprocessor 10.
FIG. 15 is a block diagram of a signal processing circuit of the reproducing side of a digital recording and reproducing device of the type described in copending application Ser. No. 08/384,878 which includes the circuit shown in FIG. 14. As shown in FIG. 15, the signal processing circuit processes signals reproduced from the recording medium for output as analog audio and video signals and also is adapted to transmit the reproduced signals over a digital transmission line via a digital interface. In FIG. 15, those components which are the same as those shown in FIG. 14 are identified by the same reference numerals and further description thereof is omitted.
The shuffling circuit 28 of FIG. 15 shuffles signals derived from the reproduced signals, as described above with reference to FIG. 14, and supplies the shuffled signals to a packetizing circuit 17 which arranges the shuffled signals into packets of predetermined size. The packets are delivered to a parity generator circuit 18 which adds parity data that is used at the remote end of the digital transmission line for detecting communication errors. The parity generator 18 supplies the packets and the parity data to a driver circuit 19 which channel codes the packets and the parity data into signals that are suitable for transmission over the digital transmission line, which may be, for example, twisted pair cable, and then serially transmits the signals over the digital transmission line via the digital interface.
FIG. 16 is a block diagram of the recording side of a known digital recording and reproducing device of the type described in the aforementioned application and which includes the circuit shown in FIG. 1 herein and in which the signals transmitted by the circuit shown in FIG. 15, for example, are received and processed for recording onto a recording medium. The apparatus shown in FIG. 16 may be connected to the remote end of the digital transmission line mentioned in connection with the signal processing circuit of FIG. 15. In FIG. 16, those components which are the same as those shown in FIG. 1 are identified by the same reference numerals and further description thereof is omitted.
As shown in FIG. 16, the signals transmitted by the signal processing circuit of FIG. 15 over the digital transmission line are received via a digital interface and supplied to a receiver circuit 21 which converts the serially transmitted signals to parallel encoded signals and then channel-decodes the signals to recover the packets. The receiver circuit 21 delivers the decoded packets to an error detecting circuit 22 which determines whether an error is present in the packets and, when an error is detected, appends an error flag to the packet. The detecting circuit 22 supplies the packets to a depacketizing circuit 23 which arranges the packets into blocks of associated video signals, blocks of associated audio signals and formatted subcode signals and delivers the signals to the switching circuit 6.
The switching circuit 6 separates the blocks of associated video signals into blocks of video signals and into blocks of VAUX signals and separates the blocks of associated audio signals into blocks of audio signals and blocks of AAUX signals for further processing by deshuffling circuit 14, parity generator 15 and channel encoder 16, for example, for subsequent recording onto a recording medium. The blocks of VAUX signals and the blocks of AAUX signals are formed of, for example, the packs shown in FIG. 8.
The switching circuit 6 also supplies the blocks of VAUX and AAUX signals to the AUX data decoder 24 which decodes accompanying audio and video information from the blocks of AAUX and VAUX signals and supplies the decoded accompanying audio and video information to the microprocessor 10 which performs various controlling operations. The microprocessor 10 delivers accompanying audio and video information to the AUX data generating circuit 11 for further processing as described above with reference to FIG. 1.
FIG. 17 is a block diagram of the recording side of a digital recording and reproducing device of the type described in the aforementioned application in which analog composite video signals are received and processed for digital recording onto the recording medium as well as for transmission over a digital transmission line. The analog composite video signals include video information and copy protection information, the latter being disposed in the vertical blanking period of the video signal for restricting the number of times the video information may be copied. FIG. 17 includes the circuit shown in FIG. 1 as well as the circuit shown in FIG. 15 which is used to transmit digital video signals over the digital transmission line and those components which have been described previously are identified by the same reference numerals.
As shown in FIG. 17, the input analog composite video signal is supplied to the A/D processing circuit 1 for further processing as described above with reference to FIG. 1. The analog composite video signal is also supplied to a vertical blanking (VBLK) signal decoder circuit 9 which decodes the copy protection information present in the vertical blanking period of the analog video signal and delivers the copy protection information to the microprocessor 10. The microprocessor 10 determines whether copying of the video information is permitted based on the copy protection information and, if copying is permitted, generates SCMS code comprising updated copy protection information that indicates that the video information was copied. The microprocessor 10 delivers the SCMS code to the AUX data generating circuit 11 which generates blocks of accompanying audio and video signals which include, for example, the packs of VAUX and AAUX signals shown in FIGS. 12A-12B and having the SCMS code. The AUX data generating circuit 11 supplies the blocks of accompanying audio and video signals to the switching circuit 6 which combines the blocks of audio signals and the blocks of accompanying audio signals to form the blocks of associated audio signals and combines the blocks of video signals and the blocks of accompanying video signals to form the blocks of associated video signals which are delivered to the deshuffling circuit 14 and further processed, as described above with reference to FIG. 1, for recording in a digital recording medium. The blocks of associated video signals, the blocks of associated audio signals and the formatted subcode signals are also supplied by the switching circuit 6 to the packetizing circuit 17 and further processed, as described above with reference to FIG. 15, for transmission over the digital transmission line via the digital interface.
FIG. 18A-18C illustrate various arrangements for dubbing a recording of, for example, video and audio information, stored on an original recording medium, such as a tape, onto one or more copy media using, for example, the recording and reproducing devices shown in FIGS. 1 and 14-17. The recording includes copy protection information for restricting the number of times that the recording may be copied, or dubbed.
FIG. 18A illustrates dubbing an original recording in which the copy protection information included therein permits the original recording to be copied. As shown in FIG. 18A, the original recording stored on a tape 40 is reproduced by a reproducing circuit 41, such as is shown FIGS. 14 or 15, and is outputted as analog audio and video signals to a recording circuit 42, such as the type shown in FIG. 17. Because copying is permitted, the reproduced recording is further processed for recording onto a copy recording medium 43. Alternatively, the reproduced recording may be outputted as digital audio and video signals via a digital transmission line from reproducing circuit 41 to the recording circuit 42 for further processing and recording onto the copy recording medium 43.
FIG. 18B illustrates the attempted dubbing of an original recording in which the copy protection information included therein does not permit copying of the original recording. The original recording stored on a tape 45 is reproduced by a reproducing circuit 46 and because copying is not permitted, the reproduced recording is not outputted to a recording circuit 47. Alternatively, the reproduced recording is outputted by the reproducing circuit 46 to the recording circuit 47, which may be of the type shown in FIG. 17, but because copying is not permitted, the recording circuit 47 does not record the reproduced recording supplied thereto onto a copy recording medium 48.
A drawback of the above-described recording and reproducing circuits is best explained in conjunction with FIG. 18C, which illustrates the attempted concurrent dubbing of an original recording onto first and second copy recording media and in which the copy protection information included in the original recording on tape 50 permits copying from the original recording but does not permit copying from a copy of that original recording. As shown in FIG. 18C, the original recording stored on tape 50 is reproduced by a reproducing circuit 51 and because copying of the original recording is permitted, the original recording is outputted to a recording and transmission circuit 52. Circuit 52 generates updated copy protection information that indicates that the video information was copied once and cannot be further copied, and this updated copy protection information is recorded with the reproduced recording onto a copy recording medium 53. Circuit 52 also transmits the updated copy protection information with the reproduced recording to the recording circuit 54, and because the updated copy protection information indicates that further copying is not permitted, the recording circuit 54 cannot record the reproduced recording onto another copy recording medium 55. As a result, concurrent dubbing of an original recording onto two or more copy recording media is not possible.